SiFive – Symposium and Workshop on RISC-V – 18 de novembro

The momentum surrounding the RISC-V Instruction Set Architecture (ISA) is growing on a global scale. SiFive, the company founded by the inventors of the RISC-V architecture, and the Polytechnic School of the University of São Paulo, are jointly hosting a Tech Symposium and Workshop on RISC-V in São Paulo on Monday, November 18, 2019. We cordially invite you to attend. This event will be highly educational and will present many opportunities for engagement within the hardware community. There will be a variety of powerful presentations by industry veterans and members of academia. Attendees will learn about the RISC-V ecosystem, and the SaaS-based approach that is enabling fast access to the custom cores, design platforms, and custom SoC solutions for emerging applications. There will also be a hands-on workshop where attendees will have the unique opportunity to configure their own RISC-V core and bring up on an FPGA.

WHERE & WHEN:

Auditorium Paulo Ribeiro Arruda

Engenharia Elétrica – Cidade Universitária

Av. Prof. Luciano Gualberto, Travessa 3, 158

Escola Politécnica da Universidade de  São Paulo

Monday, November 18, 2019

Registration opens at 8:30 a.m.

Presentations Workshop: 9:00 a.m. – 16:00 p.m. View Agenda

Lunch will be provided.

Registration is free, but seating is limited.

Please register now at: https://sifivetechsymposium.com/agenda-sao-paulo/